1. Field of the Invention
The present invention generally relates to a frequency synthesizer. More specifically, the present invention relates to a frequency synthesizer featuring high precision, wide bandwidth, low jitter, a broad frequency output range, and an integrated PLL with a limited oscillator frequency range.
2. Description of the Prior Art
Modern multimedia entertainment systems are placing ever increasing demands on the resolution, bandwidth, and switching speed of frequency synthesizers. In the past, these requirements have been satisfied by the conventional phase-locked loop (PLL) synthesizer. The fundamental advantage of PLLs has been their ability to synthesize an output clock signal of high spectral purity that may be tuned over a wide bandwidth. However, the switching speed and resolution of synthesizers are becoming critically important, and conventional PLLs are ill-suited to these applications because they suffer an inability to simultaneously provide fast frequency switching and high resolution without substantial design complexity.
Referring to FIG. 9, the classic analog PLL design comprises a phase detector 30C with two inputs and one output, which is connected to a charge pump 32C, which is in turn connected to a filter 34C, which in turn is connected to a variable-frequency oscillator 36C, which varies its frequency according to a control input. The oscillator's output is looped back through a divider 24C and into one input of the phase detector 30C, in addition to being output 62C from the circuit as a whole, optionally through a post divider 28C. The reference clock 60C is connected to the other input of the phase detector 30C, optionally through a reference clock divider 22C.
This classic design has several limitations when the input and feedback divisors are large values. First, the loop bandwidth must be significantly smaller than the phase detector input frequency in order to operate stably. Second, as a consequence of this, the filter components must be large, possibly requiring the use of external components. Third, the low bandwidth makes the PLL susceptible to noise, notably for example the standard 60 Hz power line noise. Fourth, the variable-frequency oscillator frequency limits the possible input and output frequencies of the circuit when the range of possible divisor values is large. Fifth, such a circuit may have high power consumption. Sixth, the use of external components drives up the cost of production and increases hardware space requirements.